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document:1g5-0150 rev.4 page 1 vis VG3617161BT 16mb cmos synchronous dynamic ram description the VG3617161BT is cmos synchronous dynamic ram organized as 524,288-wor d x 16-bi t x 2-bank . it is fabricated with an advanced submicron cmos technology and designed to operate from a single 3.3v power supply. this sdram is delicately designed with performance concern for current high-speed applica- tion. programmable cas latency and burst length make it possible to be used in widely various domains. it is pa c kaged by using jedec standard pinouts and standard plastic 50-pin tsop ii . features ? single 3.3v +/- 0.3v power supply ? clock frequency: 200mhz, 183mhz, 166mhz, 143mhz, 125mhz ? fully synchronous with all signals referenced to a positive clock edge ? programmable cas iatency (2,3) ? programmable burst length (1,2,4,8,& full page) ? programmable wrap sequence (sequential/interleave) ? automatic precharge and controlled precharge ? auto refresh and self refresh modes ? dual internal banks controlled by a11(bank select) ? simultaneous and independent two bank operation ? i/o level : lvttl interface ? random column access in every cycle ? x16 organization ? byte control by ldqm and udqm ? 2048 refresh cycles/32ms ? burst termination by burst stop and precharge command
document:1g5-0150 rev.4 page 2 vis VG3617161BT 16mb cmos synchronous dynamic ram pin configuration pin description (VG3617161BT) pin name function pin name function a0-a11 address inputs - row address a0-a10 - column address a0-a7 a11: bank select ldqm, udqm lower dq mask enable and upper dq mark enable dq0~dq15 data-in/data-out clk clock input ras row address strobe cke clock enable cas column address strobe cs chip select we write enable v ddq supply voltage for dq v ss ground v ssq ground for dq v dd power 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 38 37 36 35 34 33 32 31 30 29 28 27 26 v g 3 6 1 7 1 6 1 b t 50-pin plastic tsop(ii)(400 mil) v dd dq0 v ddq dq1 v ssq dq2 dq3 dq4 v ssq cas a 10 (bs)a 11 a 0 a 1 v ss dq15 v ssq dq13 v ssq dq12 v ddq dq11 clk dq8 nc udqm cke nc a8 a9 a7 a6 dq5 dq6 dq7 v ddq 23 24 25 50 49 48 47 46 45 dq14 dq10 dq9 v ddq a5 a4 v ss a 2 a 3 v dd cs 40 39 ldqm ras we
document:1g5-0150 rev.4 page 3 vis VG3617161BT 16mb cmos synchronous dynamic ram block diagram clk cke clock generator cs ras mode register column address buffer & burst counter cas we c o m m a n d d e c o d e r c o n t r o l l o g i c address row address buffer & refresh counter bank b bank a sense amplifier column decoder & latch circuit r o w d e c o d e r data control circuit dq dqm l a t c h c i r c u i t i n p u t & o u t p u t b u f f e r
document:1g5-0150 rev.4 page 4 vis VG3617161BT 16mb cmos synchronous dynamic ram absolute maximum ratings recommended dc operating conditions note 1.overshoot limit : v ih(max.) =v ddq +2.0v with a pulse width < 3ns 2.undershoot limit : v il =v ssq -2.0v with a pulse < 3ns and -1.5v with a pulse < 5ns capacitance (ta=25c,f=1mhz) parameter symbol value unit voltage on any pin relative to vss v in ,v out -1.0 to +4.6 v supply voltage relative to vss v dd ,v ddq -1.0 to +4.6 v short circuit output current i out 50 ma power dissipation p d 1.0 w operating temperature t opt 0 to + 70 j storage temperature t stg -55 to + 125 j parameter symbol min typ max unit note supply voltage v dd 3.0 3.3 3.6 v input high voltage, all inputs v ih 2.0 ?e v dd +0.3 v 1 input low voltage, all inputs v il -0.3 ?e 0.8 v 2 parameter symbol typ max unit input capacitance(clk) c 11 2.5 4 pf input capacitance(all input pins except data pins) c 12 2.5 5 pf data input/output capacitance c i/o 4.0 6.5 pf
document:1g5-0150 rev.4 page 5 vis VG3617161BT 16mb cmos synchronous dynamic ram recommended d.c. operating conditions (v dd = 3.3v 0.3v, ta = 0 ~ 70c) a.c characteristics: test conditions: (ta=0 to 70c v dd =3.3v ,v ss =0v) description/test condition symbol -5 -5.5 -6 -7 -8 unit note min. max. min. max. min. max. min. max. min. max. operating current , outputs open address changed once during t ck(min) . burst length = 1 (one bank active) i dd1 195 190 185 165 145 ma 3,4 precharge standby current in non power-down mode t ck = t ck(min) , (min) , (min) input signals are changed once during 30ns. i dd2n 105 95 85 75 65 3 precharge standby current in non power-down mode t ck = , (min) , (max) input signals are stable i dd2ns 50 45 40 35 30 precharge standby current in power-down mode t ck = t ck (min), (max) i dd2p 4 4 4 4 4 3 precharge standby current in power-down mode t ck = , (max) , (max) i dd2ps 3.5 3.5 3.5 3.5 3.5 active standby current in non power down mode (min) , t ck = t ck(min) (both bank actioe) i dd3n 90 85 75 65 55 3 active standby current in power-down (max) , t ck = t ck(min) , cs v ih(min) (both bank active) i dd3p 6 6 6 6 6 operating current (page burst, and all bank acti- vated) t ccd = t ccd(min) , outputs open, multi-bank inter- leave, gapless data i dd4 200 195 185 175 165 4,5 refresh current (min) (t ref = 32ms) i dd5 190 185 175 165 155 3 self refresh current i dd6 4 4 4 4 4 parameter description min. max. unit note i il input leakage current (all other pins not under test = ov) -5 5 a i ol output leakage current output disable, () -5 5 a v oh lvttl output ?h? level voltage (l out = -2ma) 2.4 - v v ol lvttl output ?l? level voltage (l out = 2ma) - 0.4 v t rc t rcmin () 3 csv ih 3 ckev ih 3 ckev ih 3 clkv il ckev il ckev il clkv il ckev ih 3 ckev il 3 t rc t rc 3 cke0.2v 0vv in v dd m 0vv out v ddq m 0.3v
document:1g5-0150 rev.4 page 6 vis VG3617161BT 16mb cmos synchronous dynamic ram symbol a.c. parameter 5 -5.5 -6 -7 -8 unit note min. max. min. max. min. max. min. max. min. max. t rc row cycle time 45 49.5 54 62 72 ns t rcd ras to cas delay 15 16.5 18 20 20 t rp precharge to refresh/row activate com- mand 15 16.5 18 20 20 t rrd row activate to row activate delay 10 11 12 14 16 t ras row activate to precharge time 30 100k 33 100k 36 100k 40 100k 48 100k t wr write recovery time 1tck + 3ns 1tck+ 3ns 1tck+ 2ns 1 1 clk t ck2 clock cycle time cl* = 2 - 8 8.5 10 12 ns t ck3 cl* = 3 5 5.5 6 7 8 t ch clock high time 2.3 2.3 2.3 2.5 3 t cl clock low time 2.3 2.3 2.3 2.5 3 t ac2 access time from clk (positive edge) cl* = 2 - 7 7 7 8 t ac3 cl* = 3 4.8 5 5.5 6 6 t t transition time (rise and fall) 0.5 10 0.5 10 0.5 10 0.5 10 0.5 10 t ccd cas to cas delay time 1 1 1 1 1 clk t oh data output hold time 2 2.2 2.5 2.5 2.5 ns t lz data output low impedance 1 1 2 2 2 t hz2 data output high impedance cl* = 2 4.8 5 5 6 7 9 t hz3 cl* = 3 4.8 5 5 5 7 t is data/address/control input setup time 2 2 2 2 2 t ih data/address/control input hold time 1 1 1 1 1 t srx minimum cke ?high?for self-refresh exit 1 1 1 1 1 clk t pde power down exit set-up time 5 5 5 5 6 ns t rsc (special) mode register set cycle time 2 2 2 2 2 clk t dal2 data-in to act (ref) command (cl = 2) 1clk + t rp 1clk+t rp 1clk+t rp 1clk+t rp 1clk+t rp ns t dal3 data-in to act (ref) command (cl = 3) 2clk + t rp 2clk+t rp 1clk+t rp 1clk+t rp 1clk+t rp t ref refresh time 32 32 32 32 32 ms
document:1g5-0150 rev.4 page 7 vis VG3617161BT 16mb cmos synchronous dynamic ram note: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . assume that there are only one read/write cycle during t rc (min). 4. these parameters depend on the output loading. specified values are obtained with the output open. 5. assume minimum column address update cycle t ccd (min). 6. power-up sequence is described in note 10.7. a.c. test conditions 8. transition times are measured between v ih and v il . transition (rise and fall) of input signals are fixed slope (1 ns). 9. t hz defines the time at which the outputs achieve the open circuit condition and are not reference levels. 10. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously) when all input signals are held ?nop? state and cke = ?h?, dqm = ?h?. the clk signals must be started at the same time. 2) after power-up, a pause of 200u secouds minimum is required. then, it is recommended that dqm is held ?high? (v dd levels) to ensure dq output to be in the high impedance. 3) both banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 8 auto-refresh dummy cycles must be required to stabilize the internal circuitry of the device. sequence of 4 and 5 may be changed. reference level of output signals 1.4v / 1.4v output load reference to the under output load (b) input signal levels 3.0v / 0.0v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v 3.3v 1.2k 870 30pf output lvttl d.c. test load (a) 1.4v 50 30pf output zo=50 lvttl a.c. test load (b) w w w w
document:1g5-0150 rev.4 page 8 vis VG3617161BT 16mb cmos synchronous dynamic ram basic features and function description 1.simplified state diagram self refresh mrs mode register set idle auto refresh ref a c t cke cke b s t power down active power down row active read cke cke read read suspend cke cke read a read a suspend read with auto precharge cke cke write write write suspend write a write a suspend cke cke write with auto precharge power on precharge precharge p r e ( p r e c h a r g e t e r m i n a t i o n ) p r e ( p r e c h a r g e t e r m i n a t i o n ) r e a d w i t h w r i t e w i t h a u t o p r e d h a r g e a u t o p r e c h a r g e r e a d b s t w r i t e r e a d w i t h a u t o p r e c h a r g e r e a d w i t h a u t o p r e c h a r g e write read p r e c k e c k e automatic sequence manual input note: after the auto refresh operation, precharge operation is performed automatically and enter the idle state s e l f e n t r y s e l f e x i t
document:1g5-0150 rev.4 page 9 vis VG3617161BT 16mb cmos synchronous dynamic ram 2.truth table 2.1 command truth tabl e 2.2 dqm truth table 2.3 cke truth table h : high level, l : low level x : high or low level(don?t care), v : valid data input function symbol cke cs ras cas we a11 a10 a9- a0 n-1 n device deselect desl h x h x x x x x x no operation nop h x l h h h x x x mode register set mrs h x l l l l l x v bank activate act h x l l h h v v v read read h x l h l h v l v read with auto precharge reada h x l h l h v h v write writ h x l h l l v l v write with auto precharge writa h x l h l l v h v precharge select bank pre h x l l h l v l x precharge all banks pall h x l l h l x h x burst stop bst h x l h h l x x x function symbol cke dqm n-1 n-1 u l data write/output enable enb h x l data mask/output disable mask h x h upper byte write enable/output enable enbu h x l x lower byte write enable/output enable enbl h x x l upper byte write inhibit/output disable masku h x h x lower byte inhibit/output disable maskl h x x h current state function symbol cke cs ras cas we add- ress n-1 n activating clock suspend mode entry h l x x x x x any clock suspend l l x x x x x clock suspend clock suspend mode exit l h x x x x x idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x self refresh self refresh exit l h l h h h x l h h x x x x idle power down entry h l x x x x x power down power down exit l h x x x x x
document:1g5-0150 rev.4 page 10 vis VG3617161BT 16mb cmos synchronous dynamic ram 2.4 operative command table current state cs ras cas we address command action notes idle h x x x x desl nop or power down 2 l h h x x nop or bst nop or power down 2 l h l h ba,ca,a10 read/reada illegal 3 l h l l ba,ca,a10 writ/writa illegal 3 l l h h br,ra act row active l l h l ba,a10 pre/pall nop l l l h x ref/self refresh or self refresh 4 l l l l op-code mps mode register access row active h x x x x desl nop l h h x x nop or bst nop l h l h ba,ca,a10 read/reada begin read:determine ap 5 l h l l ba,ca,a10 writ/writa begin write:determine ap 5 l l h h ba,ra act illegal 3 l l h l ba,a10 pre/pall precharge 6 l l l h x ref/self illegal l l l l op-code mrs illegal read h x x x x desl continue burst to active l h h h x nop continue burst to active l h h l x bst burst active l h l h ba,ca,a10 read/reada term burst, new read:determine ap 7 l h l l ba,ca,a10 writ/writa term burst, start write:determine ap 7,8 l l h h ba,ra act illegal 3 l l h l ba,a10 pre/pall term burst,precharging l l l h x ref/self illegal l l l l op-code mrs illegal write h x x x x desl continue burst to recovering l h h h x nop continue burst to recovering l h h l x bst burst active l h l h ba,ca,a10 read/reada term burst, start read: determine ap 7,8 l h l l ba,ca,a10 writ/writa term burst, new write:determine ap 7 l l h h ba,ra act illegal 3 l l h l ba,a10 pre/pall term burst precharging 9 l l l h x ref/self illegal l l l l op-code mrs illegal endrow ? endrow ? stoprow ? endwrite ? endwrite ? stoprow ? (1/3)
document:1g5-0150 rev.4 page 11 vis VG3617161BT 16mb cmos synchronous dynamic ram current state cs ras ca we address command action notes read with auto precharge h x x x x desl continue burst to l h h h x nop continue burst to l h h l x bst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 writ/writa illegal l l h h ba,ra act illegal 3 l l h l ba,a10 pre/pall illegal 3 l l l h x pef/self illegal l l l l op-code mrs illegal write with auto precharge h x x x x desl continue burst to recovering with auto precharge l h h h x nop continue burst to recovering with auto precharge l h h l x bst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 writ/writa illegal l l h h ba,ra act illegal 3 l l h l ba,a10 pre/pall illegal 3 l l l h x ref/self illegal l l l l op-code mrs illegal precharging h x x x x desl idle after t rp l h h h x nop idle after t rp l h h l x bst idle after t rp l h l h ba,ca,a10 read/reada illegal 3 l h l l ba,ca,a10 writ/writa illegal 3 l l h h ba,ra act illegal 3 l l h l ba,a10 pre/pall idle after t rp l l l h x ref/self illegal l l l l op-code mrs illegal row activating h x x x x desl row active after t rcd l h h h x nop row active after t rcd l h h l x bst row active after t rcd l h l h ba,ca,a10 read/reada illegal 3 l h l l ba,ca,a10 writ/writa illegal 3 l l h h ba,ra act illegal 3,10 l l h l ba,a10 pre/pall illegal 3 l l l h x ref/self illegal l l l l op-code mrs illegal endpreching arg ? endpreching arg ? endwrite ? endwrite ? nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? (2/3)
document:1g5-0150 rev.4 page 12 vis VG3617161BT 16mb cmos synchronous dynamic ram note 1. all entries assume that cke was active (high level)during the preceding clock cycle. 2. if both banks are idle, and cke is inactive(low level), the device will enter power down mode. all input buffers except cke will be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. if both banks are idle, and cke is inactive(low level), the device will enter self refresh mode. all input buffers except cke will be disabled. 5. iiiegal if t rcd is not satisfied. 6. iiiegal if t ras is not satisfied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. must mask preceding data if t dpl is not satisfied. 10. iiiegal if t rrd is not satisfied. current state cs ras ca we address command action notes write recovering h x x x x desl row active after t dpl l h h h x nop row active after t dpl l h h l x bst row active after t dpl l h l h ba,ca,a10 read/reada start read, determine ap 8 l h l l ba,ca,a10 writ/writa new write, determine ap l l h h ba,ra act illegal 3 l l h l ba,a10 pre/pall illegal 3 l l l h x pef/self illegal l l l l op-code mrs illegal write recovering with auto precharge h x x x x desl precharge after t dpl l h h h x nop precharge after t dpl l h h l x bst precharge after t dpl l h l h ba,ca,a10 read/reada illegal 3,8 l h l l ba,ca,a10 writ/writa illegal 3 l l h h ba,ra act illegal 3 l l h l ba,a10 ref/pall illegal 3 l l l h x ref/self illegal l l l l op-code mrs illegal refreshing h x x x x desl idle after t rc l h h x x nop/bst idle after t rc l h l x x read/writ illegal l l h x x act/pre/pall illegal l l l x x ref/self/mrs illegal mode register accessing h x x x x desl idle after 2 clocks l h h h x nop idle after 2 clocks l h h l x bst illegal l h l x x read/write illegal l l x x x act/pre/pall/ ref/self/mrs illegal nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? nopenter ? (3/3)
document:1g5-0150 rev.4 page 13 vis VG3617161BT 16mb cmos synchronous dynamic ram 2.5 command truth table for cke note 1. h : hight level, l : low level, x : high or low level(don't care). 2. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfie d before any command other than exit. 3. power down and self refresh can be entered only from the both banks idle state. 4. must be legal command as defined in operative command table. 5 .iiiegal if t srx is not satisfied. current state cke n-1 ras n cs ras cas we address action notes self refresh (s.r.) h x x x x x x invalid,clk(n-1)would exit s.r. l h h x x x x s.r. recovery 2 l h l h h x x s.r. recovery 2 l h l h l x x illegal 2 l h l l x x x illegal 2 l l x x x x x maintain s.r. self refresh recovery h h h x x x x idle after t rc h h l h h x x idle after t rc h h l h l x x illegal h h l l x x x illegal h l h x x x x begin clock suspend next cycle 5 h l l h h x x begin clock suspend next cycle 5 h l l h l x x illegal h l l l x x x illegal l h x x x x x exit clock suspend next cycle 2 l l x x x x x maintain clock suspend power down (p.d.) h x x x x x invalid, clk(n-1) would exit p.d. l h x x x x x exit 2 l l x x x x x maintain power down mode both banks idle h h h x x x refer to operations in operative command table h h l h x x refer to operations in operative command table h h l l h x refer to operation in operative command table h h l l l h x refresh h h l l l l op- code refer to operations in operative command table h l h x x x refer to operations in operative command table h l l h x x refer to operations in operative command table h l l l h x refer to operations in operative command table h l l l l h x self refresh 3 h l l l l l op- code refer to operations in operative command table l x x x x x x power down 3 any state other than listed above h h x x x x x refer to operations in operative command table h l x x x x x begin clock suspend next cycle 4 l h x x x x x exit clock suspend next cycle l l x x x x x maintain clock suspend p d idle ?
document:1g5-0150 rev.4 page 14 vis VG3617161BT 16mb cmos synchronous dynamic ram 3.initiallization the synchronous dram is initialized in the power on sequence. once power has been applied, a 100us minimum delay is needed in which stable power and input signals are maintained. during this delay, cke and dqm recommend to be held high. after the 100us delay, both banks must be precharged using the precharge command. once precharge is completed and the minimum t rp is satisfied, the mode register can be programmed. minimum two cbr refresh commands must be performed before or after the mode register set com- mand. 4.programming the mode register the mode register is programmed by the mode register set command using address bits a11 through a0 as data inputs. the register retains data until it is reprogrammed or until the device loses power. the mode register has four fields; options : a11 through a7 cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be asserted befor at least two clock cycles have elapsed. cas latency cas latency is the most critical parameter to be set. it tells the device how many clocks must elapse before the data will be available. the sdram is capable of reconfiguring its internal architecture based on the value of cas latency. the value is determined by the frequency of the clock and the speed grade of the device. the value can be programmed as 2 or 3. burst length burst length is the number of words that will be output or input in read or write cycle. after a read burst is completed, the output bus will become high impedance. the burst length is programmable as 1,2,4,8 or full page. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. the order is programmable as either ?sequential? or ?interleave?. the method chosen will depend on the type of cpu in the system. some microprocessor cache systems are optimized for sequential addressing and others for inter- leaved addressing. both sequences support bursts of 1,2,4 and 8. only the sequential burst. supports the full-page length.
document:1g5-0150 rev.4 page 15 vis VG3617161BT 16mb cmos synchronous dynamic ram 5.mode register 0 0 0 0 1 11 10 9 8 7 6 5 4 3 2 1 0 reserved test set x x 1 0 0 11 10 9 8 7 6 5 4 3 2 1 0 burst read and single write ltmode wt bl x x 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 mode register set ltmode wt bl x=don?t care burst length bits2-0 wt=1 wt=0 000 001 010 011 100 101 110 111 1 2 4 8 r r r full page 1 2 4 8 r r r r wrap type 0 1 sequential interleave latency bits6-4 cas iatency 000 001 010 011 100 101 110 111 r r 2 3 r r r r mode remark r:reserved
document:1g5-0150 rev.4 page 16 vis VG3617161BT 16mb cmos synchronous dynamic ram 5.1 burst length and sequence (burst of two) (burst of four) (burst of eight) full page burst is an extension of the above tables of sequential addressing, with the length being 512/ 256 words for 2mx8/1mx16 devices, respectively. starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence(decimal) 0 0,1 0,1 1 1,0 1,0 starting address (column address a1-a0, binary) sequential addressing sequence (decimal) interleave addressing sequence(decimal) 00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0 starting address (column address a2-a0, binary) sequential addressing sequence (decimal) interl eave addressing sequence(decimal) 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0
document:1g5-0150 rev.4 page 17 vis VG3617161BT 16mb cmos synchronous dynamic ram a0 a6 a5 a4 a3 a2 a1 a11 a10 a9 a8 a7 6.address bits of bank-select and precharge row (activate command) 0 select bank a ?activate? command 1 select bank b ?activate? command a0 a6 a5 a4 a3 a2 a1 a11 a10 a9 a8 a7 row (precharge) 0 0 1 result precharge bank a a11 0 1 x precharge bank b precharge all banks a10 x:don?t care a0 a6 a5 a4 a3 a2 a1 a11 a10 a9 a8 a7 col. ( cas strobes) 0 disables auto-precharge (end of burst) 1 enables auto-precharge (end of burst) 0 enable read/write commands for bank a 1 enable read/write commands for bank b
document:1g5-0150 rev.4 page 18 vis VG3617161BT 16mb cmos synchronous dynamic ram 7.precharge the precharge command can be asserted anytime after t ras(min) is satisfied. soon after the precharge command is asserted, precharge operation is performed. the synchronous dram enters the idle state after t rp(min) is satisfied. the parameter t rp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as followed. precharge in order to write all data to the memory cell correctly, the asynchronous parameter?t dpl ? must be satisfied. the t dpl( m i n .) specification defines the earliest time that a precharge command can be asserted after a write cycle. the minimum number of clocks are calculated by dividing t dpl(min.) by the clock cycle time. in summary, the precharge command can be asserted relative to the reference clock of the last valid data. in the following table, minus means clocks before the reference, plus means time after the reference. cas latency read write 2 -1 +t dpl(min.) 3 -2 +t dpl(min) burst lengh=4 clk command cas latency=2 dq command cas latency=3 dq cas latency= 2: one clock earlier than the last output data. 3: two clocks earlier than the last output data. (t ras is satisfied) hi-z q0 q3 q2 q1 pre q0 q3 q2 q1 read read t0 t1 t2 t3 t4 t5 t6 t7 pre hi-z_
document:1g5-0150 rev.4 page 19 vis VG3617161BT 16mb cmos synchronous dynamic ram 8.auto precharge d uring a read or write command cycle, a10 controls whether auto precharge is selected. if a10 is high in the read or write command (read with auto precharge command or write with auto pre- charge command), auto precharge is selected and precharging begins automatically after the burst access. in the write cycle, t dal(min.) must be satisfied to assert the next active command to the bank being pre- charged. when using auto precharge in the read cycle, knowing when the precharge starts is important because the t ras must be satisfied. once auto precharge has started, an active command to the bank can be asserted after t rp(min.) has been satisfied. the timing at which the auto precharge cycle begins depends both on the cas iatency programmed into the mode register and on whether the cycle is read or write. 8.1 read with auto precharge during a reada cycle, the auto precharge begins one clock earlier( cas iatency of 2) or two clocks earlier( cas iatency of 3) than the last data word output. read with auto precharge burst lengh=4 clk command cas latency=2 dq command cas latency=3 dq remark reada means read with auto precharge hi-z auto precharge starts qb0 qb3 qb2 qb1 reada b reada b t0 t1 t2 t3 t4 t5 t6 t7 auto precharge starts hi-z t8 qb0 qb3 qb2 qb1
document:1g5-0150 rev.4 page 20 vis VG3617161BT 16mb cmos synchronous dynamic ram 8.2 write with auto precharge during a writa cycle, the auto precharge starts at t dpl(min.) after the last data word input to the device write with auto prechrge in summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. in the table below, minus means clocks before the reference; plus means clocks after the reference. cas latency read write 2 -1 +t dpl(min.) 3 -2 +t dpl(min) burst lengh=4 clk command cas latency=2 dq command cas latency=3 dq remark writa means write with auto precharge hi-z db0 db3 db2 db1 writa b writa b t0 t1 t2 t3 t4 t5 t6 t7 hi-z_ t8 t dpl t dpl db0 db3 db2 db1 auto precharge starts auto precharge starts
document:1g5-0150 rev.4 page 21 vis VG3617161BT 16mb cmos synchronous dynamic ram 9.read/write command interval 9.1 read to read command interval when a new read command is asserted during a read cycle, it will be effective after the cas latency, even if the previous read operation has not completed. read will be interrupted by another read. a read command can be asserted in every clock without restriction. read to read command interval 9.2 write to write command interval when a new write command is asserted during a write cycle, the previous burst will be terminated and the new burst will begin with the new write command. write will be interrupted by another write. a write command can be asserted in every clock without restriction. write to write command interval burst lengh=4, cas latency=2 clk command dq qa0 qb2 qb1 qb0 read a t0 t1 t2 t3 t4 t5 t6 t7 hi-z_ t8 1 cycle qb3 read b burst lengh=4, cas latency=2 clk command dq qa0 qb2 qb1 qb0 write a t0 t1 t2 t3 t4 t5 t6 t7 hi-z_ t8 1 cycle qb3 write b
document:1g5-0150 rev.4 page 22 vis VG3617161BT 16mb cmos synchronous dynamic ram 9.3 write to read command interval the write command to read command interval is a minimum of 1 cycle. only the write data pre- ceding the read command will be written. the data bus must be in high-impedance at least one cycle prior to the first d out . write to read command interval 9.4 read to write command interval during read cycle, read can be interrupted by write. the data bus must be in high-impedance using dqm before the write command. dqm must be high at least 3 clocks prior to the write command. this restriction is necessary to avoid a data bus conflict. burst lengh=4 clk command cas latency=2 dq command cas latency=3 dq qb0 qb3 qb2 qb1 write a write a t0 t1 t2 t3 t4 t5 t6 t7 t8 qb0 qb3 qb2 qb1 1 cycle read b da0 read b da0 hi-z hi-z
document:1g5-0150 rev.4 page 23 vis VG3617161BT 16mb cmos synchronous dynamic ram read to write command interval cas latency=2 clk command dqm dq hi-z d0 d3 d2 d1 read t0 t1 t2 t3 t4 t5 t6 t7 t8 1 cycle write burst length=8, cas latency=2 clk command dqm dq q0 read t0 t1 t2 t3 t4 t5 t6 t7 t8 write t9 necessary q2 q1 d0 d2 d1 hi-z is example: burst length=4, cas latency=3 clk command dqm dq read t0 t1 t2 t3 t4 t5 t6 t7 t8 write necessary d0 d2 d1 hi-z is q2 the minimum command interval = (4+1) cycles
document:1g5-0150 rev.4 page 24 vis VG3617161BT 16mb cmos synchronous dynamic ram 10.burst termination there are two methods to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. 10.1 burst stop command during a read burst. when the burst stop command is asserted, the burst read outputs are terminated and the data bus goes to high-impedance after the cas latency from the burst stop command. during a write burst. when the burst stop command is asserted, any data provided at that cycle will not be written. the burst write is effectively terminated and no further data can be written until a new write command is asserted. burst termination remark bst: burst stop command remark bst: burst stop command burst lengh=x, cas intency=2,3 clk command cas latency=2 dq cas latency=3 dq q0 q2 q1 read t0 t1 t2 t3 t4 t5 t6 t7 bst hi-z q0 q2 q1 hi-z burst lengh=x, cas latency=2,3 clk command cas latency=2,3 dq q0 q2 q1 write t0 t1 t2 t3 t4 t5 t6 t7 bst hi-z_ q0
document:1g5-0150 rev.4 page 25 vis VG3617161BT 16mb cmos synchronous dynamic ram 10.2 precharge termination 10.2.1 precharge termination in read cycle during a read cycle, the burst read operation can be terminated by a precharge command. when the precharge command is asserted, the burst read operation is termi- nated and precharge starts. read data will remain valid until one clock( cas latency of 2)or two clocks( cas latency of 3) after the precharge command and the same bank can be activated again after t rp(min) from the precharge command. precharge termination in read cycle burst lengh= x clk command cas latency=2 dq hi-z read t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp pre act dq read pre act t rp cas latency=3 q0 q3 q2 q1 hi-z q0 q3 q2 q1 command
document:1g5-0150 rev.4 page 26 vis VG3617161BT 16mb cmos synchronous dynamic ram 10.2.2 precharge termination in write cycle during a write cycle, the burst write operation can be terminated by a precharge command. when the precharge command is asserted, the burst write operation in imme- diately terminated and precharge starts. the same bank can be activated again after trp(min.) from the precharge command. the dqm must be high to mask invalid data in. when cas latency is 2 or 3, the data written prior to the precharge command will be cor- rectly stored. however, invalid data may be written at the same clock as the precharge com- mand. to prevent this from happening, dqm must be high at the same clock as the precharge command. this will mask the invalid data. precharge termination in write cycle burst lengh = x clk command cas latency=2 dqm hi-z write t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp pre act dq write pre act t rp cas latency=3 hi-z d0 d3 d2 d1 d0 d3 d2 d1 dqm d4 d4 command dq
document:1g5-0150 rev.4 page 27 vis VG3617161BT 16mb cmos synchronous dynamic ram timing diagram
document:1g5-0150 rev.4 page 28 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 key t rsc t rp hi-z precharge command all banks mode register set command command clk cke cs cas we a11(bs) a10 ras a0-a9 dqm dq mode register set
document:1g5-0150 rev.4 page 29 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 ac parameters for write timing (1 of 2) t ckh begin auto precharge bank b begin auto precharge bank a t ck2 t cks t cms t cmh t as t ah t t rc rcd t rrd t dal t ch t cl raa rba rab rac rbb rbb rac cab rab cba rba caa raa daa0 daa1 daa2 daa3 dba0 dba1 dba2 dba3 dab0 dab1 dab2 dab3 t ds t d h t dpl t rp activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write with auto precharge command bank a precharge command bank a activate command bank a activate command bank b clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq burst length=4, cas latency=2
document:1g5-0150 rev.4 page 30 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t ch t cl t cks t cms t cmh raa raa t as t ah caa rba rba cba rab cab rac rab rac begin auto precharge bank a begin auto precharge bank b t ckh t ck3 ac parameters for write timing (2 of 2) clk cke cs ras cas we a11(bs) a10 a0~a9 dqm dq t rcd t rrd t rc t dal daa0 daa1 daa2 daa3 dba0 dba1 dba2 dba3 dab0 dab1 dab2 dab3 activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write without auto precharge command bank a t ds t dh t dpl rp t precharge command bank a activate command bank a burst length=4, cas latency=3
document:1g5-0150 rev.4 page 31 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 ac parameters for read timing (1 of 2) clk cke cs ras cas we a11(bs) a10 a0-a9 dqm dq burst length=2, cas latency=2 t ch t cl t ck2 begin auto precharge bank b t ckh t cks t cms t cmh t ah t as raa rba rab rab cba rba caa raa t rrd t ras t rc t rcd t ac2 t lz t oh t ac2 t oh t hz t rp t hz hi-z activate command bank a read command bank a activate command bank b read with auto precharge bank b precharge command bank a activate command bank a qaa0 qaa1 qba0 qba1
document:1g5-0150 rev.4 page 32 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 ac parameters for read timing (2 of 2) clk cke cs ras cas we a11(bs) a10 a0-a9 dqm dq burst length=2, cas latency=3 t lz t hz hi-z activate command bank a read command bank a activate command bank b read with auto precharge bank b precharge command bank a activate command bank a t ch t cl t cks t ck3 t cms t cmh t ah t as raa raa caa rba rba cba rab rab t rrd t ras t rc t rp t rcd t ac3 t oh t ac3 qaa0 qaa1 qba0 qba1 t oh t hz command t ckh begin auto precharge bank b
document:1g5-0150 rev.4 page 33 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 power on sequence and auto refresh (cbr) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq high level is required minimum of 2 refresh cycles are required t rsc t rp high level is necessary t rc address key inputs be stable for 100us precharge all banks must command 1st auto command refresh 2nd auto refresh command mode set command command register
document:1g5-0150 rev.4 page 34 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clock suspension during burst read (using cke) (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t hz activate bank a command read bank a command clock 2 cycles hi-z qaa0 qaa1 qaa2 qaa3 raa caa raa t ck2 clock suspended 1 cycle suspended clock 3 cycles suspended burst length=4, cas latency=2
document:1g5-0150 rev.4 page 35 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clock suspension during burst read (using cke) (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t hz activate bank a command read bank a command clock 2 cycles hi-z qaa0 qaa1 qaa2 qaa3 raa raa t ck3 clock suspended 1 cycle suspended clock 3 cycles suspended burst length=4, cas latency=3 caa
document:1g5-0150 rev.4 page 36 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clock suspension during burst write (using cke) (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq activate bank a command write bank a command clock 2 cycles hi-z raa caa raa t ck2 clock suspended 1 cycle suspended clock 3 cycles suspended burst length=4, cas latency=2 qaa0 qaa1 qaa2 qaa3
document:1g5-0150 rev.4 page 37 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 clock suspension during burst write (using cke) (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t raa raa t ck3 burst length=4, cas latency=3 caa activate bank a command write bank a command clock 2 cycles hi-z clock suspended 1 cycle suspended clock 3 cycles suspended qaa0 qaa1 qaa2 qaa3
document:1g5-0150 rev.4 page 38 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 power down mode and clock mask clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq raa raa t ck2 burst length=4, cas latency=2 activate bank a command power down mode entry power down bank a hi-z active standby read clock mask caa t cks t ckh valid t cks raa qaa0 qaa1 qaa2 qaa3 mode exit command start clock mask end t hz precharge command power down mode entry precharge standby power mode down exit command
document:1g5-0150 rev.4 page 39 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto refresh (cbr) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4, cas latency=2 precharge all banks command cbr refresh hi-z cbr refresh command activate command read raa caa raa q0 q1 q2 q3 command command t rp t rc t rc
document:1g5-0150 rev.4 page 40 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 self refresh (entry and exit) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t srx all banks self refresh hi-z self refresh exit self refresh entry exit t rc t cks t srx t pde t rc must be idle self refresh exit activate command
document:1g5-0150 rev.4 page 41 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random column read (page within same bank)(1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4, cas latency=2 precharge bank a command read hi-z activate read raa qad0 command command raa caa raa cab cac rad rad cad qaa0 qaa1 qaa2 qaa3 qab0 qab1 qac0 qac1 qac2 qac3 qad1 qad2 qad3 bank a read command bank a read command bank a precharge command bank a bank a command bank a
document:1g5-0150 rev.4 page 42 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random column read (page within same bank)(2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=4, cas latency=3 activate bank a command read hi-z activate read command command raa caa raa cab cac rad cad qac2 qac3 qaa0 qaa1 qaa2 qaa3 qab0 qab1 qac0 qac1 bank a read command bank a precharge command bank a bank a command bank a rad read command bank a
document:1g5-0150 rev.4 page 43 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random column write (page within same bank) (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4, cas latency=2 activate bank b command write hi-z activate write command command rba cba raa cbb cbc rbd cbd dbc2 dbc3 dba1 dba2 dba3 dbb0 dbb1 dbc0 dbc1 bank b write command bank b precharge command bank b bank b command bank b write command bank b rad dbd2 dbd3 dbd0 dbd1 dba0
document:1g5-0150 rev.4 page 44 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random column write (page within same bank) (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=4, cas latency=3 activate bank b command write hi-z activate command rba cba rba cbb cbc rbd cbd dbc2 dbc3 dba1 dba2 dba3 dbb0 dbb1 dbc0 dbc1 bank b write command bank b precharge command bank b command bank b write command bank b rbd dbd2 dbd0 dbd1 dba0 write command bank b
document:1g5-0150 rev.4 page 45 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random row read (interleaving banks) (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=8, cas latency=2 activate bank b command read hi-z command rba qaa0 qaa1 qba1 qba2 qba3 qba4 qba5 qba6 qba7 bank b activate command bank a active command bank b read command bank a qbb1 qbb0 qba0 read command bank b qaa3 qaa4 qaa5 qaa6 qaa7 qaa2 precharge command bank b raa rbb rba cba raa caa rbb cbb t rcd t ac2 t rp high
document:1g5-0150 rev.4 page 46 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random row read (interleaving banks) (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=8, cas latency=3 activate bank b command read hi-z command rba qaa0 qaa1 qba1 qba2 qba3 qba4 qba5 qba6 qba7 bank b activate command bank a precharge command bank b qbb0 qba0 read command bank b qaa3 qaa4 qaa5 qaa6 qaa7 qaa2 read command bank a raa rba cba raa caa cbb t rcd t ac3 t rp high rbb rbb activate bank b command precharge command bank b
document:1g5-0150 rev.4 page 47 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random row write (interleaving banks) (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=8, cas latency=2 activate bank a command write hi-z command raa qba0 qba1 qaa1 qaa2 qaa3 qaa4 qaa5 qaa6 qaa7 bank a activate command bank b active command bank a write command bank b dab3 dab2 qaa0 write command bank a qba3 qba4 qba5 qba6 qba7 qba2 precharge command bank a rba rab raa caa rba cba rab cab t rcd t rp high t dpl t dpl dab0 dab1 dab4 precharge command bank b
document:1g5-0150 rev.4 page 48 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 random row write (interleaving banks) (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=8, cas latency=3 activate bank a command write hi-z command daa7 dba0 daa0 daa1 daa2 daa3 daa4 daa5 daa6 bank a activate command bank b dab2 dab1 activate command bank a dba2 dba3 dba4 qba5 dba6 dba1 write command bank b raa rba t rcd t rp high t dpl t dpl dbb7 dab0 dab3 write command bank a raa rba rab caa rba rab cba cab precharge command bank a precharge command bank b
document:1g5-0150 rev.4 page 49 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read and write cycle (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4, cas latency=2 activate bank a command write hi-z command dab3 qac0 qaa0 qaa1 qaa2 qaa3 dab0 dab1 bank a write command bank a read command bank a qac3 qac1 the read data the write data is masked with a zero clock raa raa cab cac caa latency is masked with two clocks latency
document:1g5-0150 rev.4 page 50 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 read and write cycle (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=4, cas latency=3 activate bank a command read hi-z command dab3 qac0 qaa0 qaa1 qaa2 qaa3 dab0 dab1 bank a write command bank a qac3 qac1 the read data the write data is masked with a zero clock raa latency is masked with two clock latency raa cab caa cac read command bank a
document:1g5-0150 rev.4 page 51 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 interleaved column read cycle (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4, cas latency=2 activate bank a command read hi-z command qbb1 qbd0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 bank a read command bank b qbd2 qbd1 precharge raa rba raa cab rba cba cbb cbc cab cbd qab1 qbc0 qbc1 qbd3 activate command bank b read command bank b qbb0 qab0 read command bank b read command bank a read command bank b precharge command bank a command bank b t rcd t ac2
document:1g5-0150 rev.4 page 52 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 interleaved column read cycle (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z qbb1 qab2 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qab3 precharge raa rba raa caa rba cba cbb cbc cab qab1 qbc0 qbc1 read command bank a read command bank b qbb0 qab0 read command bank b read command bank b read command bank a precharge command bank b command bank a t rrd activate command bank b t rcd t ac3
document:1g5-0150 rev.4 page 53 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 interleaved column write cycle (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z dbb1 dbd0 daa0 daa1 daa2 daa3 dba0 dba1 dbd1 precharge raa rba raa caa rba cba cbb cbc cab dab1 dbc0 dbc1 write command bank a write command bank b dbb0 dab0 command write command bank b write command bank a precharge command bank a command bank b t rrd activate command bank b t rcd t rp cbb dbd2 dbd3 write bank b t dpl write command bank b
document:1g5-0150 rev.4 page 54 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 interleaved column write cycle (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z dbb1 dad0 daa0 daa1 daa2 daa3 dba0 dba1 qad1 precharge raa rba raa caa rba cba cbb cbc cab dab1 dbc0 dbc1 write command bank a write command bank b dbb0 dab0 write command bank b write command bank b write command bank a write command bank b command bank a t rrd activate command bank b t rcd cbd t dpl t rp qad2 qad3 t dpl precharge command bank b
document:1g5-0150 rev.4 page 55 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto precharge after read burst (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z qba3 qbb0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qbb1 read with raa rba caa rba cba cab rbb cbb qab3 qab0 qab1 activate command bank b qba2 qab2 read with command bank a activate command bank b read with command bank b activate command bank a command bank a read with auto precharge bank a rac qbb2 qbb3 rbb rac raa cac qac0 qac2 read bank a command command qac1 auto precharge auto precharge auto precharge start auto precharge bank b start auto precharge bank a start auto precharge bank b high
document:1g5-0150 rev.4 page 56 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto precharge after read burst (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z qba3 qbb0 qaa0 qaa1 qaa2 qaa3 qba0 qba1 qbb1 raa rba raa qab3 qab0 qab1 read command bank a read with command bank b qba2 qab2 read with command bank a activate command bank b read with command bank b activate command bank b qbb2 qbb3 rbb rba cba cbb caa rbb cab auto precharge auto precharge auto precharge start auto precharge bank b start auto precharge bank a start auto precharge bank b high
document:1g5-0150 rev.4 page 57 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto precharge after write burst (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4, cas latency=2 activate bank a command hi-z dba3 dbb0 daa0 daa1 daa2 daa3 dba0 dba1 dbb1 raa rba raa dab3 dab0 dab1 write command bank a write with command bank b dba2 dab2 write with command bank a activate command bank b write with command bank b activate command bank b dbb2 dbb3 rbb rba cba cbb caa rbb cab auto precharge auto precharge auto precharge start auto precharge bank b start auto precharge bank a start auto precharge bank b high rac rac cac dac0 dac1 dac2 dac3 activate command bank a write with auto precharge bank a start auto precharge bank a
document:1g5-0150 rev.4 page 58 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 auto precharge after write burst (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=4, cas latency=3 activate bank a command hi-z dba3 daa0 daa1 daa2 daa3 dba0 dba1 raa rba raa dab3 dab0 dab1 write command bank a write with command bank b dba2 dab2 write with command bank a activate command bank b dbb0 rba cba caa rbb cab auto precharge start auto precharge bank b start auto precharge bank a start auto precharge bank b high rbb cbb dbb1 dbb2 dbb3 activate command bank b write with auto precharge auto precharge command bank b
document:1g5-0150 rev.4 page 59 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page read cycle (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command read hi-z command raa qaa+1 bank a the burst counter wraps burst stop read command bank b qaa full page burst operation does not raa caa rbb t rp high activate command bank b rba rbb cba qaa+2 qaa-2 qaa-1 qaa qaa+1 qba qba+1 qba+2 qba+3 qba+4 qba+51 qba+6 activate command bank b from the highest order page address back to zero during this time interval terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address command precharge command bank b rba
document:1g5-0150 rev.4 page 60 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page read cycle (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=full page, cas latency=3 activate bank a command read hi-z command raa qaa+1 bank a the burst counter wraps burst stop read command bank b qaa full page burst operation raa caa rbb t rp high activate command bank b rba rbb cba qaa+2 qaa-2 qaa-1 qaa qaa+1 qba0 qba+1 qba+2 qba+3 qba+4 qba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not teminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address rba
document:1g5-0150 rev.4 page 61 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page write cycle (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command write hi-z command raa daa+1 bank a the burst counter wraps burst stop write command bank b daa full page burst operation raa caa rbb t bdl high activate command bank b rba rbb cba daa+2 daa+3 daa-1 daa daa+1 dba dba+1 dba+2 dba+3 dba+4 dba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address dba+6 data is ignored rba
document:1g5-0150 rev.4 page 62 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page write cycle (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=full page, cas latency=3 activate bank a command write hi-z command raa daa+1 bank a the burst counter wraps burst stop write command bank b daa full page burst operation raa t bdl high activate command bank b daa+2 daa+3 daa-1 daa daa+1 dba dba+1 dba+2 dba+3 dba+4 dba+5 activate command bank b from the highest order page address back to zero during this time interval command precharge command bank b does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address rba rbb caa rba cba rbb data is ignored.
document:1g5-0150 rev.4 page 63 vis VG3617161BT 16mb cmos synchronous dynamic ram hi-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 byte write operation clk cke cs ras c as we a11(bs) a10 a0~a9 ldqm udqm t ck2 burst length=4, cas latency=2 hi-z raa raa high activate caa cab caz dq0~dq7 command bank a read command bank a upper byte is masked lower byte is masked write command bank a write upper is masked read command bank a lower byte is masked lower byte is masked dq8~dq15
document:1g5-0150 rev.4 page 64 vis VG3617161BT 16mb cmos synchronous dynamic ram hi-z t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 burst read and single write operation clk cke cs ras c as we a11(bs) a10 a0~a9 ldqm udqm t ck2 burst length=4, cas latency=2 hi-z raa raa high activate caa cab cad dq0~dq7 command bank a read command bank a single write single write read command bank a lower byte is masked upper byte is masked dq8~dq15 cac cae command bank a command bank a single write command bank a lower byte is masked
document:1g5-0150 rev.4 page 65 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page random column read clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command activate hi-z command raa qba0 bank b read command bank b qaa0 raa activate command bank b qab0 qab1 qbb0 qbb1 qac0 qac1 qac2 qbc0 qbc1 qbc2 read command bank a precharge cbc cac rbb rba rba caa cba cab cbb rbb t rp read command bank b read command bank a read command bank a read command bank b command bank b (precharge termination)
document:1g5-0150 rev.4 page 66 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 full page random column write clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=full page, cas latency=2 activate bank a command activate hi-z command raa qba0 bank b write command bank b qaa0 raa activate command bank b qab0 qab1 qbb0 qbb1 qac0 qac1 qac2 qbc0 qbc1 qbc2 write command bank a precharge cbc cac rbb rba rba caa cba cab cbb rbb t rp write command bank b write command bank a write command bank a write command bank b command bank b (precharge termination) write data is masked
document:1g5-0150 rev.4 page 67 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 precharge termination of a burst (1 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck2 burst length=4,8 or full page, cas latency=2 activate bank a command write hi-z command raa bank a activate command bank a read command bank a rac cab rab rab rac precharge termination of a write burst. write data is masked. precharge command read command bank a precharge command bank a precharge termination high raa cac caa qaa1 qaa0 qaa2 da3 qab0 qab1 qab2 qac0 qac1 qac2 t dpl t rp t rp t rp bank a of a read burst. activate command bank a precharge command bank a
document:1g5-0150 rev.4 page 68 vis VG3617161BT 16mb cmos synchronous dynamic ram t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 precharge termination of a burst (2 of 2) clk cke cs ras c as we a11(bs) a10 a0~a9 dqm dq t ck3 burst length=4,8 or full page, cas latency=3 activate bank a command write hi-z command raa bank a activate command bank a cab rab rab rac precharge command read command bank a high raa rac caa daa1 daa0 qab0 qab1 qab2 qab3 t dpl t rp bank a activate command bank a activate command bank a t rcd t ras t rp write data is masked precharge termination of a write burst. precharge termination of a read burst.
document:1g5-0150 rev.4 page 69 vis VG3617161BT 16mb cmos synchronous dynamic ram ordering information VG3617161BT- 6 ? vg ? vis memory product ? 36 ? technology/design rule ? 17161 ? device type/configuration ? b ? mask/design version ? t ? package type, t: tsop ? 6 ? cycle time, 5: 5.5ns, 6: 6ns, 7: 7ns, 8: 8ns packaging information ? 400mil, 50-pin plastic tsop p art number frequency@cl3 package VG3617161BT-5.5 VG3617161BT-6 VG3617161BT-7 vg3617161b t- 8 180mhz 166mhz 143mhz 125mhz 400mil 50-pin plastic tsop d 1 25 e zd 0.100(0.004) 48- e b a seating plane detail a 50 e1 26 c detail a a1 a2 rad r l 0 x ~5 x b b rad r1 allowable dambar protrusion shall not cause the lead to 3. dimension b does not include dambar protrusions/intrusion. interlead protrusion shall not exceed 0.25mm(0.01") per side. mold protrusion shall not exceed 0.15mm(0.006") per side. 2. dimension d does not include mold protrusion. 1. controlling dimension : millimeters note: than the min b dimension by more than 0.07mm. dambar intrusion shall not cause the lead to be narrower be wider than the max b dimension by more than 0.13mm. dimension e1 does not include interlead protrusion. 0.010 0.004 0.25 0.11 r b1 b c1 c with plating base metal section b-b r1 0.11 --- --- --- 0.004 --- --- --- 0.875 ref. 0.80 basic l 0.40 e1 10.03 e e 11.56 zd 0.12 c 20.82 d c1 0.11 b1 0.30 b 0.30 0.0344 ref. 0.0315 basic 0.60 10.29 0.50 10.16 0.016 0.395 11.96 11.76 0.455 0.024 0.405 0.020 0.400 0.471 0.463 0.005 0.21 21.08 0.16 20.95 --- --- 0.820 0.0045 0.40 0.45 --- --- 0.012 0.012 0.008 0.830 0.006 0.825 --- --- 0.016 0.018 --- --- millimeters 0.05 a1 a2 0.95 a --- dim min. 1.20 1.05 0.15 --- 1.00 --- 0.002 0.037 --- max. nom. min. 0.047 0.041 0.006 0.039 --- --- max. inches nom.

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